1. Technical Field
This invention relates in general to semiconductor memories and, more specifically, to semiconductor memories in which local phase signals are generated in local phase drivers using global phase signals and local isolation signals, thus eliminating the need to route section signals to the local phase drivers.
2. State of the Art
As shown in FIG. 1, a conventional Dynamic Random Access Memory (DRAM) 10 includes multiple 256 Kilobit (KB) sub-arrays 12 accessed using even and odd row decoders 14 and 16, sense amplifiers 18, gap circuitry 20, center circuitry 22, and address circuitry 24. More specifically, accessing one of the sub-arrays 12 begins when the address circuitry 24 receives a memory address (not shown) and outputs section signals SECTION, global isolation signals GISO, and global phase signals GPH in response. Referring to FIG. 2 for a moment, the center circuitry 22 receives the section signals SECTION and the global isolation signals GISO and gates them together in local isolation (LISO) circuitry 26 to produce local isolation signals LISO. Referring now to FIG. 3, the gap circuitry 20 receives the section signals SECTION and the global phase signals GPH and gates them together in local phase drivers 28 to produce local phase signals LPH. The local phase signals LPH are then used in conjunction with the memory address (not shown) by one of the row decoders 14 and 16 to fire a selected row in one of the sub-arrays 12. Once the selected row is fired, the local isolation signals LISO are used in one of the sense amplifiers 18 in conjunction with the memory address (not shown) to access a selected column in the same sub-array 12 as the selected row.
As can be seen in FIG. 1, many signals must be routed to the gap circuitry 20 and sense amplifiers 18, including the section signals SECTION, the local isolation signals LISO, and the global phase signals GPH. These signals use "real estate" on the die on which the DRAM 10 is fabricated, and thus limit the functional circuitry that can be implemented in the DRAM 10, or increase the necessary size of the die on which the DRAM 10 is fabricated. Thus, it would be desirable to reduce the signals routed to the gap circuitry 20 and sense amplifiers 18 in order to increase the functional circuitry that can be implemented in the DRAM 10 or decrease the necessary size of the die on which the DRAM 10 is fabricated.
Therefore, there is a need in the art for a semiconductor memory having a reduced number of signals routed to gap circuitry and sense amplifiers.